Dr. Chin-Long Wey

Vice President & Direction General

National Chip Implementation Center

National Applied Research Laboratories

 

E-mail：clwey@cic.org.tw

Phone：+8863-577-3693 ext. 121

Secretary：Ms. Shu-Wan Sung       E-mail：may@cic.org.tw

Phone：+8863-577-3693 ext. 126  FAX：+8863-6687078

Address: 7F, No.26, Prosperity Rd. 1, Science Park, Hsinchu City, Taiwan.

網頁裝飾藍色三角形小圖Current Positions：

Vice President & Direction General, National Chip Implementation Center, National Applied Research Laboratories (2007/7-present)

TSMC Distinguished Chair Professor, Department of Electrical Engineering, National Central University (2003/8-present)

網頁裝飾藍色三角形小圖Education：

Ph.D in Electrical Engineering, Texas Tech University, Lubbock, Texas (1983)

MS in Computer Science, Texas Tech University, Lubbock, Texas (1980)

BS in Mathematics, National Central University, Jhongli, Taiwan (1973)

網頁裝飾藍色三角形小圖Professional Experience：

2003/8-2006/7

Dean, College of Electrical Engineering and Computer Science, National Central University

1983/8-2003/8

Professor, Department of Electrical and Computer Engineering, Michigan State University, E. Lansing, Michigan.

2001/9-2002/9

Co-Founder & President, JMicron Technology Corporation, Hsinchu

1995/8-1997/8

Founding Director, Computer Engineering Program, College of Engineering, MSU.

網頁裝飾藍色三角形小圖Research：

Design and Test of Integrated Circuits, Fault-tolerant Systems, Design for Reliability and Yield.

網頁裝飾藍色三角形小圖Honors and Awards

l        Distinguished Research Fellow, National Applied Research Laboratories (2007~)

l        TSMC Distinguished Chair Professor, National Central University (2004~)

l        Chair Professor, Department of Electronics Engineering, National Yunlin University of Science and Technology (2003)

 

 

List of Publication

Book Chapters

1.        Wey, C.L., Wu, C.-c., and R. Saeks, "Analog Fault Diagnosis," Testing and Diagnosis of VLSI and ULSI, Ed. by M. Sami and F. Lombardi, Kluwer Academic Publisher, pp.117-150, 1988.

2.        Lombardi, F. and C.L. Wey, "On Front Reconfiguration of VLSI Arrays," Testing and Diagnosis of VLSI and ULSI, Ed. by M. Sami and F. Lombardi, Kluwer Academic Publisher, pp.429-468, 1988.

3.        Wey, C.L. and R. Saeks, "On the Implementation of Analog ATPG: The Linear Case," Analog Fault Diagno­sis, Edited by R.W. Liu, IEEE PRESS, 1989.

4.        Wey, C.L., "A Searching Approach Self-Testing Algorithm for Analog Fault Diagnosis," Testing and Diagno­sis of Analog Circuits and Systems, Ed. by R.W. Liu, Van Nostrand Reinhold, New York, pp.147-185, 1991.

5.        Wey, C.L., "Test techniques for CMOS Switched-Current Circuits," Analog and Mixed-Signal Test, Edited by B. Vinnakota, Prentice-Hall, Inc., 1998.

  

Journal Papers

1         Wu, C.-c., Nakajima, K., Wey, C.L., and R. Saeks, "Analog Fault Diagnosis with Failure Bounds," IEEE Trans. on Circuits and Systems, Vol. CAS-29, No.5, pp.277-284, May 1982.

2         Wey, C.L. and R. Saeks, "On the Implementation of Analog ATPG: The Linear Case," IEEE Trans. on Instru­mentation and Measurement, Vol. IM-34, No.3, pp.442-449, September 1985.

3        Wey, C.L., "A Decision Process for Analog System Fault Diagnosis," IEEE Trans. on Circuits and Systems, Vol. CAS-34, No.1, pp.107-109, January 1987.

4        Wey, C.L., Vai, M.K., and F. Lombardi, "On the Design of a Redundant PLA," IEEE Journal of Solid-State Circuits. Vol. SC-22, No.1, pp.114-117, February 1987.

5        Wey, C.L. and F. Lombardi, "On the Repair of Redundant RAM’s," IEEE Trans. on CAD of Integrated Cir­cuits and Systems. Vol. CAD-6, No.2, pp.222-231. March, 1987.

6        Wey, C.L. and F. Lombardi, "On the Novel Self-test Approach to Digital Test," The Journal of Computers, Vol.30, No.3, pp.258-267, March 1987.

7        Wey, C.L., "Design of Testability for Analog Fault Diagnosis," International Journal of Circuit Theory and Application, Vol.15, No.2, pp.123-142, April 1987.

8        Lombardi, F. and C.L. Wey, "Algorithms for Functional Testing of Digital Systems," (Invited Paper) Interna­tional Journal of Electronics, Vol.62, No.5, pp.707-732, May 1987.

9        Jiang, B.L., Wey, C.L., and L.J Fan, "Fault Prediction for Analog Circuits," Journal of Circuits, Systems, and Signal Process. Vol.7, No.1, pp.95-109, January 1988.

10     Chan, S.-W. and C.L. Wey, "The Design of Concurrent Error Diagnosable Systolic Arrays for Band-Matrix Multiplication," IEEE Trans. on CAD of Integrated Circuits and Systems (Special issue on Testable and Maintainable Design), Vol. CAD-7, No.1, pp.21-37, January 1988.

11     Chan, S.-W., Leung, S.S., and C.L. Wey, "A Systematic Design Strategy for Concurrent Error Diagnosable It­erative Logic Arrays," IEE Proceedings, Part E, Computers and Digital Techniques, Vol.135, No.2, pp.87- 94, March 1988.

12     Wey, C.L., "On Yield Considerations for the Design of Redundant Programmable Logic Arrays," IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. CAD-7, No.4, pp.528-535, April 1988.

13     Wey, C.L. and R. Saeks, "On the Implementation of Analog ATPG: The Nonlinear Case," IEEE Trans. on In­strumentation and Measurement, Vol. IM-37, No.2, pp.252-258. June 1988.

14     Wey, C.L., "Parallel Processing for Analog Fault Diagnosis," International Journal of Circuit Theory and Ap­plication, Vol.16, pp.303-316, July 1988.

15     Jiang, B.L., and C.L. Wey, "Fault Prediction Process for Large Analog Circuit Networks," International Jour­nal of Circuit Theory and Application. Vol.17, No.2, pp.141-149, April 1989.

16     Wey, C.L. and S.M. Chang, "Test Generation for C-testable Array Dividers," IEE Proceedings, Part E, Com­puters and Digital Techniques, Vol.136, No.5, pp.434-442, September 1989.

17     Chang, T.Y., and C. L. Wey, "Design of fault diagnosable and repairable PLA," IEEE Journal of Solid-State Circuits. Vol. SC-24, No.5, pp.1451-1454, October 1989.

18     Wey, C.L., and T.Y. Chang, "An Efficient Output Phase Assignment for PLA Minimization," IEEE Trans. on CAD of Integrated Circuits and Systems, Vol.9, No.1, pp.1-7, January 1990.

19     Wey, C.L., "Built-In Self-Test (BIST) Structure for Analog Circuits Fault Diagnosis," IEEE Trans. on Instru­mentation and Measurement. Vol. IM-39, No.2, pp.517-521, June 1990.

20     Wey, C.L., and T.Y. Chang, "Design of VLSI-Based Parallel Multipliers," IEE Proceedings, Part E, Comput­ers and Digital Techniques. Vol.137, No.4, pp.328-336, July1990.

21     Jiang, B.L., and C.L. Wey, "Fault Prediction for Analog Circuits - Reply," Journal of Circuits, Systems, and Signal Process. Vol.9, No.4, p.503, 1990.

22     Wey, C.L., Chang, T.Y., and J.Y. Ding, "Design of Fault Diagnosable and Repairable Folded PLAs for Yield Enhancement," IEEE Journal of Solid-State Circuits. Vol.26, No.1,pp.54-57, January 1991.

23     Wey, C.L., "Alternative Built-In Self-Test Structure (BIST) for Analog Circuit Fault Diagnosis," Electronics Letters. Vol.27, No.18, pp.1627-1628, August 1991.

24     Wey, C.L., "Concurrent Error Detection in Current-Mode A/D Converter," Electronics Letters. Vol.27, No.25, pp.2370-2372, December 1991.

25     Wey, C.L., "Concurrent Error Detection in Array Dividers by Alternating Input Data," IEE Proceedings, Part E, Computers and Digital Techniques. Vol.139, No.2, pp.123-130, March 1992.

26     Wey, C.L., and S. Krishnan, "An Accurate Current-mode Divide-by-two Circuit," Electronics Letters. Vol.28, No.9, pp.820-822, April 1992.

27     Wey, C.L., and S. Krishnan, "Built-In Self-Test (BIST) Structures for Analog Circuit Fault Diagnosis with Cur­rent Test Data," IEEE Trans. on Instrumentation and Measurement, Vol. IM-41, No.4, pp.535-539, August 1992.

28     Wey, C.L., Krishnan, S., and S. Sahli, "Design of Concurrent Error Detectable Current-Mode A/D converters for Real-time Applications," Analog Integrated Circuits and Signal Processing, No.4, pp.65-74, July 1993.

29     Krishnan S., and C.L. Wey, "An Accurate Reference-generating Circuit for Successive Approximation Current- mode A/D Converters," International Journal of Circuit Theory and Application. No.21, pp.361-369, August 1993.

30     Shieh, M.D., Wey, C.L., and P.D. Fisher, "Fault Effects in Asynchronous Sequential Logic Circuits," IEE Pro­ceedings, Part E, Computers and Digital Techniques. Vol. 140, No.6, pp.327-332, November 1993.

31     Kang, J.-W., Fisher, P.D., and C.L. Wey, "An Efficient Modeling and Synthesis Procedure of Asynchronous Sequential Logic Circuits," IEE Proceedings, Part E, Computers and Digital Techniques. Vol.141, No.1, pp. 61-64, January 1994.

32     Wey, C.L., Berthlot, N, and B. Veltkamp, "Concurrent Error Detection in High Speed Carry-free Dividers," IEE Proceedings, Computers and Digital Techniques, Vol.141, No.6, pp.356-360, November 1994

33     Lai, C.S., and C.L. Wey, "SOLiT: An Automated system for Synthesizing Reliable Sequential Circuits with Multi-level Logic Implementation," IEE Proceedings, Computers and Digital Techniques, Vol.142, No.1, pp.49-54, January 1995.

34     Huang, R., and C.L. Wey, "Simple Yet Accurate Current Copiers for Low-Voltage Current-Mode Signal Pro­cessing Applications," International Journal of Circuit Theory and Application, vol.23, pp.137-145, No.2, March 1995.

35     Wey, C.L., "Design and Test Generation of C-testable High Speed Dividers," IEE Proceedings, Computers and Digital Techniques,.Vol.142, No.3, pp.193-200, May 1995.

36     Kang, J.-W., Wey, C.L., and P.D. Fisher, "Applications of Bipartite Graphs for Race-free State Assignment," IEEE Trans. on Computers, Vol.44, No.8, pp. 1002-1011, August 1995.

37     Wey, C.L., Krishnan, S., and S. Sahli, "Test Generation and Concurrent Error Detection in Current-Mode A/D Converters," IEEE Trans. on CAD, Vol. 14, No.10, pp. 1291-1298, October 1995.

38     Huang, R., and C.L. Wey, "Simple Low-Voltage, High-speed, High-Linearity V-I Converter with S/H for An­alog Signal Processing Applications," IEEE Trans. on Circuits and Systems. Part II. Analog and Digital Sig­nal Processing. Vol.43, No.1, pp.52-55, January 1996.

39     Wey, C.L., "Built-In Self-Test (BIST) Design of High-Speed Carry-free Dividers," IEEE Trans. on VLSI Sys­tems, Vol. 4, No. 1, pp. 141-145, March 1996.

40     Huang, R., and C.L. Wey, "Design of High-speed, High-accuracy Current Copiers for Low-Voltage Analog Signal Processing Applications," IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Processing. Vol.43, No.12, pp.836-839, December 1996.

41     Wey, C.L., "Built-in Self-Test (BIST) Design of Current-mode Algorithmic A/D Converter," IEEE Trans. on Instrumentation and Measurement. Vol. 46, No. 3, pp.667-671, June 1997.

42     Pan, T.-H, and C.L. Wey, "GRASS: an Efficient Gate re-assignment Algorithm for Inverter Minimization in Post Technology Mapping," IEE Proceedings, Computers and Digital Techniques. Vol. 144, No.5, pp.348- 352, September 1997.

43     Wang, C.-P., and C.L. Wey, "Fault Macromodel for Switches in Switched-Current Circuits," International Journal of Circuit Theory and Application. Vol. 26, pp.93-102. January 1998.

44     Huang, R., and C.L. Wey, "A High-performance CMOS Oversampling Current Sample/Hold (S/H) Circuit Us­ing Feedforward Approach," IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Pro­cessing, Vol. 45, No.3, pp. 395-399. March 1998.

45     Huang, W-H., and C.L. Wey, "ATPRG: An Automatic Test Program Generator Using HDL-A for Fault Diag­nosis of Analog/Mixed-Signal Integrated Circuits," IEEE Trans. on Instrumentation and Measurement., Vol. 47, No. 2, pp.426-431, April 1998.

46     Huang, W.-H., and C.L. Wey, "Diagnosability Analysis of Analog Circuits," International Journal of Circuit Theory and Application. Vol. 26, No.5, pp.439-451, September 1998.

47     Wey, C.L., and M.-D. Shieh, "Design of High-Speed Square Generator," IEEE Trans. on Computers.  Vol.47, No. 9, pp.1021-1026, September 1998.

48     Wang, J.-S., and C.L. Wey, "Design and Analysis of High Performance Current Reference Generators for Low- Power CMOS Data Converters," IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Processing. Vol.46, No.5, pp.647-652, May 1999.

49     Wang, J.-S., and C.L. Wey, "A 12-bit, 100ns/b, 1.9mW CMOS Switched-Current Cyclic A/D Converter," IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Processing, Vol.46, No.5, pp.507- 516, May 1999

50     Wan, Y., and C.L. Wey, "Efficient Algorithms for Binary Logarithmic Conversion and Addition," IEE Proceedings, Computers and Digital Techniques. Vol.146, No.3, pp.168-176, May 1999.

51     Wey, C.L. and C.-P. Wang, "A Fast Radix-4 SRT Divider and Its VLSI Implementation," IEE Pro­ceedings, Computers and Digital Techniques. Vol. 146, No.4, pp.205-210, July 1999.

52     Wey, C.L., and W.-H. Huang, "Designability Check for Analog Circuits with Incomplete Implementation In­formation," IEEE Trans. on Circuits and Systems, Part I, Fundamental Theory and Applications. Vol. 46, No.8, pp.939-949, August 1999.

53     Wan, Y., Khalil, M.A, and C.L. Wey, "Efficient Conversion Algorithms for Long-Word-Length Binary Log­rithmic Numbers and Hardware Implementation," IEE Proceedings, Computers and Digital Techniques. Vol. 146, No.6, pp.295-301, November 1999.

54     Huang, R., Wang, J.-S., and C.L. Wey, "A Fully Differntial Current Copier for Performance Improvement," In­ternational Journal of Circuit Theory and Application. Vol. 28, No.2, pp. 101-108, March 2000.

55     Wang, C.-P., and C.L. Wey, "Design of High performance Current Comparator as Built-In Testers of CMOS Switched-Current  Circuits," International Journal of Analog Integrated Circuits and Signal Processing, Vol.23, No.3, pp.179-188, June 2000.

56     Wey, C.L., "Design of Fast High-Radix SRT Dividers and Their VLSI Implementation," IEE Proceedings, Computers and Digital Techniques, Vol.147, No.4, pp.275-282, July 2000.

57     Wey, C.L., “ReSTRO: Efficient Rectlinear Steiner Tree Construction with Rectangular Obstacles,” WSEAS Trans. on Circuits and Systems, Vol.5, pp.1768-1774, December 2006.

58     Wey, C.L., S.-Y. Lin, T.-H. Tsai, and M.T. Shiue, “Efficient Implementation of Interpolation Technique for Symbol Timing Recovery in DVB-T Transceiver Design,” WSEAS Trans. on Circuits and Systems, Vol. 6, pp.215-221, Feburary 2007.

59     Wey, C.L., and S.-Y. Lin, “An Efficient Pipelined Divider with a Small Lookup Table,” WSEAS Trans. on Electronics, Vol. 4, pp.56-52, March 2007.

60     Wey,C.L., C.-S. Huang, and S. Quan, “Design of Reliable CMOS Phase Locked Loops,” International Journal of Electrical Engineering, Vol.14, No.3, pp.195-206, 2007.

61     Luo, P.-W., Chen, J.-E, Wey, C.L., Cheng, L.-C., Chen, J.-J., and W.-C. Wu, “Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” IEEE Trans. on CAD of Integrated Circuits and Systems, Vol.27, No.11, pp.2097-2101, November 2008.

62     Wey, C.L., M.-D. Shieh, and S.-Y. Lin, “Efficient Algorithm and Hardware Implementation of Finding First Two Minimum Values for LDPC Decoding Applications,” IEEE Trans. on Cicuits and Systems I. (in presess)

63     Luo, P.-W., Chen, J.-E, and C.L. Wey, “Yield Evaluation of Mixed-Signal Circuits Using Spatial Correlation Analysis,” SoC Technical Journal, ITRI, Taiwan. (in presess)

 

Conference Papers

 1. Wu, C.-c., Nakajima, K., Wey, C.L., and R. Saeks, "Analog fault diagnosis with failure bounds," Proc. 24th Midwest Symp. on Circuits and Systems, Albuquerque, NM, pp.515-520, June 1981.

 2.   Wey, C.L., Holder, D., and R. Saeks, "On the Implementation of an Analog ATPG," Proc. IEEE 3rd Automatic Test Program Generation (ATPG) workshop, pp.33-36, San Francisco, CA, March, 1983.

 3. Wey, C.L., Holder, D. and R. Saeks, "On the Implementation of an Analog ATPG," Proc. IEEE international Symp. on Circuits and Systems. Newport Beach, CA, pp.1102-1105, May 1983.

 4. Wey, C.L., and R. Saeks, "On the Implementation of Analog ATPG II," IEEE 4th Automatic Test Program Gen­eration (ATPG) workshop, Washington D.C., February 1984.

 5. Wey, C.L., and R. Saeks, "On the Implementation of an Analog ATPG: The Nonlinear Case," Proc. IEEE In­ternational Symp. on Circuits and Systems, Montreal, Canada, pp.213-216, May 1984.

 6. Wey, C.L., "Parallel Processing for Analog Fault Diagnosis," Proc. 27th Midwest Symp. on Circuits and Sys­tems, Morgantown, WV, pp.435-438, June 1984.

 7. Wey, C.L., "UUT Modeling for Digital Test - A Self-Test Approach," Proc. IEEE Fourth Annual Phoenix Con­ference on Computers and Communications, Phoenix, AZ, pp.312-316, March 1985.

 8. Wey, C.L., "Design of Testability for Analog Fault Diagnosis," Proc. IEEE International Symp. on Circuits and Systems, Kyoto, Japan, pp.515-518, June 1985.

 9. Lombardi, F., and C.L. Wey, "Fault Identification Algorithm for VLSI Systems," Proc. ICCD, International Conference on Computer Design: VLSI in Computers, Port Chester, NY, pp. 693-696, October 1985.

10. Lombardi, F., and C.L. Wey, "On a Multiprocessor System with Dynamic Redundancy," Proc. Real-Time Sys­tems Symposium, San Diego, CA. pp. 3-12, December 1985.

11. Lombardi, F., and C.L. Wey, "Diagnosis and Fault Identification Algorithms for Large Scale Computing Sys­tems," Proc. First International Conference on Supercomputing Systems, Tarpon Spring, FL, pp. 404-413. Dec.ember 1985.

12. Wey, C.L., and F. Lombardi, "On a New Decision Process for t-diagnosis of an Analog System," Proc. IEEE International Symp. on Circuits and Systems, San Jose, CA, pp.1255-1256, May 1986.

13. Jiang, B.L., and C.L. Wey, "Multiple Fault Diagnosis with Failure Bound for Analog Circuits," Proc. IEEE In­ternational Symp. on Circuits and Systems, San Jose, CA, pp.1261-1264, May 1986.

14.    Wey, C.L., and F. Lombardi, "On the Repair of Programmable Logic Arrays," Proc. IEEE International Symp. on Circuits and Systems, San Jose, CA, pp.649-652, May 1986.

15.    Wey, C.L., Chang, T.Y., and M.K. Vai, "On the Design of Fault-Tolerant Programmable Logic Arrays," Proc. International Computer Symp., Tainan, Taiwan, pp.398-404, December 1986.

16.    Wey, C.L., "An Efficient Unrepairability Detection Scheme for Redundant RAM Test System," Proc. Interna­tional Computer Symp., Tainan, Taiwan, pp.406-413, December 1986.

17.    Wey, C.L., and F. Lombardi, "Efficient, Yet Simple Algorithms for Repairing Redundant RAMs," Proc. IEEE International Symp. on Circuits and Systems, Philadelphia, PA, pp. 871-874, May 1987.

18.    Wey, C.L., and F. Lombardi, "Analysis and Design of Repairable PLAs," Proc. CompEuro, pp.363-366, May 1987.

19.    Wey, C.L., "On Yield Considerations for the Design of Redundant Programmable Logic Arrays," Proc. ACM/ IEEE Design Automation Conference (DAC), pp.622-628, June 1987.

20.  Jiang, B.L., and C.L. Wey, "Fault Prediction Process for Large Analog Circuit Networks," Proc. 30th Midwest Symp. on Circuits and Systems, pp. 132-135, August 1987.

21.    Wey, C.L., Chang, T.Y., and Y.F. Chen, "The Design of VLSI-Based Parallel Multipliers," Proc. 30th Midwest Symp. on Circuits and Systems, pp.97-104, August 1987.

22.   Chang, S.M., and C.L. Wey, "Test Generation for C-testable Array Multipliers," Proc. 25th Allerton Confer­ence, Univ. of Illinois. pp. 1040-1049, Sept. 1987

23.   Wey, C.L., and T.Y. Chang, "Minimization of PLAs with Ground True Outputs," Proc. of 25th ACM/IEEE De­sign Automation Conference (DAC), Anaheim, CA. pp.421-426, June 1988.

24.   Chang, T.Y. and C.L. Wey, "Design and Test of Electrically Field-Repairable APLAs," Proc. 31st Midwest Symp. on Circuits and Systems, St. Louis, MO, pp.36-39, August 1988.

25.   Wey, C.L., and T.Y. Chang, "An Efficient Boolean Comparison Process for Logic Verification," Proc. 31st Midwest Symp. on Circuits and Systems, St. Louis, MO, pp.1175-1178, August 1988.

26.   Wey, C.L., Jiang, B.L., and G. Wierzba, "Built-In Self-Test for Analog Circuit Networks," Proc. 31st Midwest Symp. on Circuits and Systems, St. Louis, MO, pp.862-865, August 1988.

27.   Wey, C.L. and S.M. Chang, "Built-In Self-Test (BIST) Design of C-Testable Baugh-Wooley Array Multiplier," Proc. 31st Midwest Symp. on Circuits and Systems. St. Louis, MO. pp.1186-1189, August 1988.

28.   Wey, C.L., and S.M. Chang, "Test Generation of C-testable Array Dividers," Proc. IEEE International Confer­ence on Computer Design: VLSI in Computers & Processors (ICCD ’88), Port Chester, NY, pp.140-144, Oc­tober 1988.

29.   Wey, C.L., and B.L. Jiang, "Built-In Self-Test (BIST) Design of Large Scale Analog Circuit Networks," Proc. 1989 IEEE International Symp. on Circuits and Systems, Portland, OR, pp.2048-2051, May 1989.

30.   Wey, C.L., Chang, S.M., and J.Y. Jou, "An Efficient Output Phase Assignment for MultiLevel Logic Minimi­zation," Proc. 1989 International Workshop on Logic Synthesis, North Carolina, May 1989.

31.   Wey, C.L., "Fault Location in Repairable Programmable Logic Arrays," Proc. IEEE International Test Confer­ence (ITC), Washington, D.C. pp.679-685, August 1989.

32.   Wey, C.L., Chang, S.M., and J.Y. Jou, "OPAM: An Efficient Output Phase Assignment for Multilevel Logic Minimization," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’89), Cambridge, MA, pp.270-273. October 1989.

33.   Wey, C.L., "Output Phase Assignment for Logic Minimization," (invited), 2nd Workshop on CAD for VLSI, Taiwan, March, 1990.

34.   Wey, C.L., Ding, J. and T.Y. Chang, "Design of Repairable and Fully Diagnosable Folded PLAs for Yield En­hancement," Proc. 27th ACM/IEEE Design Automation Conf. (DAC), Orlando, FL, pp.327-332,  June 1990.

35.   Wey, C.L., and J. Ding, "Design of Repairable and Fully Testable Folded PLAs for Yield Enhancement," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’90), Cam­bridge, MA, pp.112-115, September 1990.

36.   Wey, C.L., and T.Y. Chang, "On the Design of Concurrent Error Detectable Multiply and Divide Arrays," Proc. International Computer Symposium, Hsinchu, Taiwan, ROC, pp.564-570, December 1990.

37.   Wey, C.L., "Concurrent Error Detection in Array Dividers by Alternating Input Data," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’91), Cambridge, MA, pp.114-117, October 1991.

38.   Wey, C.L., Shieh, M.-D., and P.D. Fisher, "On Synthesis for Testability of Asynchronous Sequential Logic Cir­cuits," IFIP International Workshop on the Relationship between Synthesis, Test, and Verification. Berkeley, CA, November 1991.

39.    Lai, C.S., and C.L. Wey, "An efficient Algorithm for Reducing Hardware Overhead in Self-Checking Circuits and Systems," Proc. 35th Midwest Symp. on Circuits and Systems, Washington, D.C., pp.1538-1541, August 1992.

40.    Kang, J.W., Wey, C.L., and P.D. Fisher, "An Efficient Modelling and Synthesis Procedure of Asynchronous Sequential Logic Circuits," Proc. 35th Midwest Symp. on Circuits and Systems, Washington, D.C., pp.512-515, August 1992.

41.    Shieh, M.D., Wey, C.L., and P.D. Fisher,"Model of Asynchronous Finite State Machines and Their Pipelined Structures," Proc. 35th Midwest Symp. on Circuits and Systems, Washington, D.C., pp.659-662, August 1992.

42.    Krishnan, S., Sahli, S., and C.L. Wey, "Test Generation and Concurrent Error Detection in Current-Mode A/D converters," Proc. IEEE International Test Conference (ITC), Baltimore, MD., pp. 312-320, September 1992.

43.    Sahli, S., Krishnan, S., and C.L. Wey, "Design of Concurrent Error Detectable Current-Mode A/D converters," Proc. International Conference on Microelectronics, Tunisia, pp.1.1.1.1-4, December 1992.

44.    Kang, J.-W., Wey, C.L., and P.D. Fisher, "Race-free State Assignments Using Bipartite Graphs," Proc. of IEEE Symposium on Circuits and Systems, Chicago, pp.2560-2563. May 1993.

45.   Shieh, M.D., Wey, C.L., and P.D. Fisher, "Scan Design for Asynchronous Sequential Logic Circuits Using SR- latches," Proc. 36th Midwest Symp. on Circuits and Systems, Detroit, August 1993.

46.   Kang, J.-W., C.L. Wey, and P.D. Fisher, "A Synthesis Procedure for Large-Scale Asynchronous Finite State Machines," Proc. 36th Midwest Symp. on Circuits and Systems, Detroit, August 1993.

47.   Lai, C.S., and C.L. Wey, "Design of Fast, Yet Low Hardware Cost Self-Testing Berger Code Checkers," Proc. 36th Midwest Symp. on Circuits and Systems, Detroit, August 1993.

48.   Wey., C.L., M.-D. Shieh, and P.D. Fisher, "ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’93), Cambridge, MA, pp. 159-162, October 1993.

49.   Huang, R., and C.L., Wey, "A Simple Yet Accurate Current Copier," Proc. 37th Midwest Symp. on Circuits and Systems, Lafayette, LA, pp. 121-124, August 1994.

50.   Wey, C.L., "Design of C-testable High Speed Dividers," Proc. 37th Midwest Symp. on Circuits and Systems, Lafayette, LA, pp. 261-264, August 1994.

51.   Krishnan, S., and C.L. Wey, "A Parallel Current-mode A/D Converter Array with a Common Current Refer­ence-Generating Circuit," Proc. 37th Midwest Symp. on Circuits and Systems, Lafayette, LA, pp.1168-1171, August 1994.

52.   Wey, C.L., "Concurrent Error Detection in High Speed Carry-free Dividers," Proc. IEEE International Confer­ence on Computer Design: VLSI in Computers & Processors (ICCD ’94), Cambridge, Massachusetts, pp. 124- 127, October 1994.

53.   Huang, R., and C.L. Wey, "High-Speed, Low Voltage V-I Converters for Analog Signal Processing Applica­tions," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS’ 94), Taipei, Taiwan, pp. 494-498, December 1994

54.   Wey, C.L., "Built-In Self-Test (BIST) Design of High-Speed Carry-free Dividers," Proc. IEEE Symposium on Circuits and Systems, Seattle, WA, pp.1916-1919, May 1995.

55.   Wey, C.L., Tetelbaum, A.Y., and T. Bickart, "A Performance-driven Placement Approach of Standard Cells," Proc. International Conference on Intelligent Systems, Gelengick, Russia, pp.31-35, September 1995.

56.   Wey, C.L., Wang, H., and C.P. Wang, "A Self-timed Redundant-Binary to Binary Number Converter for Digital Arithmetic Processors," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Pro­cessors (ICCD ’95), Austin, TX, pp. 386-389, October 1995.

57.   Pan. T.-H., Kay, H.-S, Chun, Y., and C.L. wey, "High-Radix SRT Division with Speculation of Quotient Dig­its," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’95), Austin, TX, pp.479-482, October 1995.

58.   Huang, R., and C.L. Wey, "A High-Accuracy CMOS Oversampling Current Sample/Hold (S/H) Circuit Using Feedforward Approach," Proc. IEEE International Symposium on Circuits and Systems, Atlanta, GA, Vol. I, pp.65-68, May 1996.

59.   Huang, R., and C.L. Wey, "A 5mW, 12-b, 50ns/b Switched-current Cyclic A/D Converter," Proc. IEEE Inter­national Symposium on Circuits and Systems, Atlanta, GA, Vol. I, pp.207-210, May 1996.

60.   Wang, C.-P., Hatzopoulos, A.A., and C.L. Wey, "A Test Paradigm for Analog and Mixed-signal Circuits and Systems," Proc. IEEE International Symposium on Circuits and Systems, Atlanta, GA, Vol. III, pp. 194-197, May 1996.

61.   Wang, C-.P., and C.L. Wey, "Test Generation of Switched-current A/D Converters," Proc. 2nd IEEE Interna­tional Mixed Signal Testing Workshop, Quebec City, Canada, pp. 98-103, May 1996.

62. Huang, R., Wang, C.-P., Grunewald, C., and C.L. Wey, "Design of High-Accuracy CMOS Oversampling Cur­rent Sample/Hold (S/H) circuits," Proc. of 39th Midwest Symp. on Circuits and Systems, Iowa, 939-942, Au­gust 1996.

63.   Wey, C.L., and C.-P. Wang, "VLSI Implementation of a Fast Radix-4 SRT Division," Proc. of 39th Midwest Symp. on Circuits and Systems, Iowa, pp.65-68, August 1996.

64.   Pan, T.H., and C.L. Wey, "An Efficient Gate Re-assignment Algorithm in Post Technology Mapping," Proc. of 39th Midwest Symp. on Circuits and Systems, Iowa, pp.363-366, August 1996.

65.   Wey, C.L., "On Design of Efficient Square Generator," IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’96), Austin, TX, pp. 506-513, October 1996.

66.   Wey, C.L., "Mixed-Signal Testing -- a Review," (invited) IEEE International Conference on Electronics, Cir­cuits, and Systems, Rodos, Greece, pp.1064-1067, October 1996.

67.   Wang, C.-P. and C.L. Wey, "Test Generation of Analog Switched-Current Circuits," Proc. Asian Test Sympo­siums, Taiwan, pp.376-381, November 1996.

68.   Wang, C.-P., and C.L. Wey, "Efficient Testability Design Methodologies for Mixed-Signal/Analog Integrated Circuits,"