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(揭祘絪腹A002-BA002CIC揭祘腹璣ゅダB辫Ω腹)
(I) Full-Custom IC Design某揭祘
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揭祘嘿
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揭祘ず甧
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| (A001)Full-Custom IC Design kit(WS) | 膀娄揭祘 |
| (A002)Composer | 砞璸吏挂ざ残 |
| (A003)Layout Implementation | Layout |
| (A004)Layout Techniques for Mix-Signal IC | Layout Techniques |
| (A006)Dracula | Layout Verification |
| (A007)HSPICE | Timing Simulation |
| Option
(A204)TimeMill/PowerMill/PathMill |
Timing Simulation
/ Power Simulation .. |
PCㄏノ
(A005)Full-Custom IC Design kit (PC)
(A004)Layout Techniques
for Mix-Signal IC
(II) Cell-Based IC Design某揭祘
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揭祘嘿
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揭祘ず甧
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| (A101)Cell-Based IC Design kit | 膀娄揭祘 |
| (A102)Verilog ┪
(A103)VHDL |
RTL Level or Gate Level Simulation |
| (A107)Debussy | Verilog or VHDL盎岿硁砰 |
| (A105)Logic Synthesis
(Synopsys) ┪ (A106)Ambit (Cadence) |
Logic Synthesis |
| (A201)Cell-Based IC
Physical Design (SE) ┪ (A202)Cell-Based IC Physical Design (Apollo) |
Floorplan, Placement & Routing |
| (A204)TimeMill/PowerMill/PathMill | Timing/Power Simulation .. |
(III) FPGA or CPLD Design某揭祘
Xilinx (A302) Xilinx (PC) の(A303) Xilinx-HDL(PC)
Altera (A301)Altera (PC)
Option
(A304) FPGA Synthesizer
(IV)MM/RF IC Design某揭祘
(A501) GaAs Foundry
(A601) MMIC Design
(A503) Harmonica
(A504) Symphony (linearnonlinear
system simulation)
(V)IC Testing某揭祘
(A402) IC Testing
(VI)DSP闽烩办砞璸:
(A104) SPW/HDS
Last Updated 2001/12/20
癩刮猭瓣產龟喷╯皘 瓣產垂╰参砞璸いみ
| 穝λ跋 300 穝λ厩堕跋甶穨隔腹加(垂いみ) | Tel:(03)5773693,Fax:(03)5774064 |
| 玭跋 744 玭郡穝カ秏吏狥隔琿312腹1F | Tel:(06)5053041,Fax:(06)5053044 |