揭某

程穝 ヘ魁 穓碝 絬癚阶跋 郎更 faq
back

 

揭祘某

 

 

(揭祘絪腹A002-BA002CIC揭祘腹璣ゅダB辫Ω腹)

(I) Full-Custom IC Design某揭祘
 
揭祘嘿
揭祘ず甧
(A001)Full-Custom IC Design kit(WS) 膀娄揭祘
(A002)Composer 砞璸吏挂ざ残
(A003)Layout Implementation Layout
(A004)Layout Techniques for Mix-Signal IC Layout Techniques
(A006)Dracula Layout Verification 
(A007)HSPICE Timing Simulation 
Option

(A204)TimeMill/PowerMill/PathMill

Timing Simulation 

/ Power Simulation ..

PCㄏノ

(A005)Full-Custom IC Design kit (PC)

(A004)Layout Techniques for Mix-Signal IC

(II) Cell-Based IC Design某揭祘
 
揭祘嘿
揭祘ず甧
(A101)Cell-Based IC Design kit  膀娄揭祘
(A102)Verilog
(A103)VHDL
RTL Level or 
Gate Level Simulation
(A107)Debussy Verilog or VHDL盎岿硁砰
(A105)Logic Synthesis (Synopsys)
(A106)Ambit (Cadence)
Logic Synthesis
(A201)Cell-Based IC Physical Design (SE)
(A202)Cell-Based IC Physical Design (Apollo)
Floorplan, Placement & Routing
(A204)TimeMill/PowerMill/PathMill Timing/Power Simulation ..

(III) FPGA or CPLD Design某揭祘

Xilinx (A302) Xilinx (PC) (A303) Xilinx-HDL(PC)

Altera (A301)Altera (PC)

Option

(A304) FPGA Synthesizer


(IV)MM/RF IC Design某揭祘

(A501) GaAs Foundry

(A601) MMIC Design

(A503) Harmonica

(A504) Symphony (linearnonlinear system simulation)


(V)IC Testing某揭祘

(A402) IC Testing


(VI)DSP闽烩办砞璸:

(A104) SPW/HDS
 

Last Updated 2001/12/20

cic.gif

癩刮猭瓣產龟喷╯皘 瓣產垂╰参砞璸いみ
穝λ跋 300 穝λ厩堕跋甶穨隔腹加(垂いみ) Tel:(03)5773693,Fax:(03)5774064
玭跋 744 玭郡穝カ秏吏狥隔琿312腹1F Tel:(06)5053041,Fax:(06)5053044